Abdel Ejnioui
Assistant Professor
Department of Electrical and Computer
Engineering
Office: ENGR I 250
Office Phone: 407.823.4757
Dept Fax: 407.823.5835
E-Mail: aejnioui@mail.ucf.edu
Education
1999:
Ph.D., Computer Science & Engineering,
1995:
M.S., Computer Science,
1992:
B.S., Engineering Technology,
Professional Experience
2001
– Present: Assistant Professor,
2001
– 2001: Software Architect, Xnext Inc.,
2000
– 2001: Lecturer,
1999
– 2000: Software Engineer, Avanti Corp.,
1997
– 1999: Research Assistant,
Publications
Journal
Publications
A.
Alsharqawi, A. Ejnioui, “A Clockless Pipelining Technique Based on Self-Resetting
Stage Logic”, submitted to the IEEE
Transactions on Circuits and Systems, available as UCF Technical Report UCF-ECE-0501.
A.
Ejnioui, A. Alsharqawi, “Coarse-Grain
Clockless Pipelining Based on Self-Resetting Stage
Logic”, submitted to the Journal of
Circuits, Systems, and Computers, available as UCF Technical Report UCF-ECE-0407.
A.
Ejnioui, M. Lomonaco,
“CRYPTARRAY: A Scalable and Reconfigurable Architecture for Cryptographic
Applications”, submitted to the Journal
of Circuits, Systems, and Computers, available as UCF Technical Report UCF-ECE-0406.
R.
DeMara, Y. Tseng, A. Ejnioui,
“Performance Evaluation of Hierarchy Annotation and Credit Distribution
Quiescence Mechanisms”, submitted to the Journal
of Distributed Computing, available as UCF Technical Report UCF-ECE-0405.
R.
DeMara, Y. Tseng, A. Ejnioui,
“Tiered Algorithm for Distributed Process Quiescence and Termination Detection”,
submitted to the IEEE Transactions on
Parallel and Distributed Systems, available as UCF Technical Report UCF-ECE-0402.
R. DeMara, Y. Tseng, K. Drake, A. Ejnioui, “Capability Classes of Barrier Synchronization Techniques”, submitted to the International Journal of Parallel and Distributed Systems and Networks, available as UCF Technical Report UCF-ECE-0403.
A.
Ejnioui, N. Ranganathan, “Routing
on Field-Programmable Switch Matrices”, IEEE
Transactions on VLSI Systems, vol.
11, no. 2, Apr. 2003, pp. 283-287.
A.
Ejnioui, N. Ranganathan, “Multi-terminal
Net Routing for Partial Crossbar-Based Multi-FPGA Systems”, IEEE Transactions on VLSI Systems, vol. 11, no. 1, Feb. 2003, pp. 71-78.
A.
Ejnioui, N. Ranganathan, “A
Partitioning Algorithm for Technology-Mapped Designs on Single-Chip Emulation Systems”,
IEEE Transactions on VLSI Systems, vol. 9, no. 2, April 2001, pp. 407-410.
V.
Krishna, N. Ranganathan, A. Ejnioui, “A
Tree Matching Chip”, IEEE
Transactions on VLSI Systems, vol. 7, no. 2, pp. 277-280, June 1999.
Conference Publications
A.
Ejnioui, R. DeMara, “Area
Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices”,
accepted in the International Conference
on Engineering of Reconfigurable Systems and Algorithms, 2005.
A. Alsharqawi, A. Ejnioui, “Synthesis
of Self-Resetting Stage Logic Pipelines”, accepted in the IEEE Computer Society Annual Symposium on
VLSI, 2005.
A.
Ejnioui, A. Alsharqawi,
“Pipeline-Level Control of Self-Resetting Pipelines”, Euromicro Symposium on Digital System Design, pp. 342-349, 2004.
A.
Ejnioui, A. Alsharqawi, “Pipeline-Level
Control of Self-Resetting Stage Logic Pipelines”, IEEE Northeast Workshop on Circuits and Systems, pp. 389-392, 2004.
A.
Ejnioui, A. Alsharqawi, “A Clockless Reconfigurable Array Based on Self-Resetting
Logic”, 8th World Multiconference on Systemics,
Cybernetics, and Informatics, vol. 11, pp. 61-66, 2004.
A.
Ejnioui, A. Alsharqawi, “Self-Resetting
Stage Logic Pipelines”, Proc. of the
ACM
A.
Ejnioui, A. Alsharqawi,
“Pipeline Design Based on Self-Resetting Stage Logic”, Proc. of the IEEE Computer Society Annual Symposium on VLSI, pp.
254-257, 2004.
A.
Ejnioui, A. Rhiati, “A
Reconfigurable Memory Management Core for Java Applications”, Proc. of the IEEE Computer Society Annual
Symposium on VLSI, pp. 309-312, 2004.
R.
Namballa,
K.
Sitaraman, A. Ejnioui, N. Ranganathan, “A Parallel
Algorithm and Architecture for Object Recognition in Images”, Proc. of the IEEE Computer Architecture for Machine Perception,
2003.
W.
Kuang, J. S. Yuan, A. Ejnioui, “Supply
Voltage Scalable System Design Using Self-Timed Circuits”, Proc. of the IEEE Computer Society Annual Symposium on VLSI, pp.
161-166, 2003.
S.
Krishna, N. Ranganathan, A. Ejnioui, “A
VLSI Architecture for Object Recognition Using Tree Matching”, Proc. of
the International Conference on Application-Specific Systems, Architectures and
Processors, pp. 325-334, 2002.
A.
Ejnioui, N. Ranganathan, “Routing
on Switch Matrix FPGAs”, Proc. of the 13th
International Conference on VLSI Design, pp. 248-253, 2000.
A.
Ejnioui, N. Ranganathan, “Design
Partitioning on Single-Chip Emulation Systems,” Proc. of the
International Conference on VLSI Design, pp. 234-239, 2000.
A.
Ejnioui, N. Ranganathan, “Multi-Terminal
Net Routing for Partial Crossbar-Based Multi-FPGA Systems”, Proc. of the ACM International Symposium on FPGAs, pp. 176-184, 1999.
V.
Krishna, A. Ejnioui, N. Ranganathan, “A
Tree Matching Chip”, Proc. of the
International Conference on VLSI Design, pp. 280-285, 1996.
A. Ejnioui, N. Ranganathan, “Systolic Algorithms for Tree Pattern Matching”, Proc. of the International Conference on Computer Design: VLSI in Computers and Processors, pp 650-655, 1995.
Professional Activities
Reviewer
for the IEEE Transactions on VLSI
Reviewer
for the IEEE Transactions on Circuits and Systems for Video Technology
Reviewer
for the Journal of Applied Systems Studies
Reviewer
for the Journal of Mathematical and Computer Modeling
Reviewer
for the International Conference on Computer Design
Reviewer
for the International VLSI Design Conference
Treasurer
for the IEEE Computer Society Annual Symposium on VLSI
Member
of the IEEE
Current Students
Abdelhalim M. Alsharqawi, Ph.D. student
Rashad Oreifej, Ph.D. student
Anuja Thakkar, M.S. student
Hamzah Issa, M.S. student